One or more embodiments disclosed herein relate to semiconductor devices, and more particularly, to a delay locked loop (DLL) circuit capable of reducing jitter, and a semiconductor device including the DLL circuit.
Synchronous semiconductor devices, such as synchronous DRAMs (SDRAMs), operate in synchronization with a reference clock provided from an external source or operate an internal circuit at timing having a predetermined phase relation with the phase of the reference clock. Accordingly, a timing clock generation circuit is installed in the synchronous semiconductor device.
In a synchronous semiconductor device, a DLL circuit is used as the timing clock generation circuit to remove an influence of a propagation delay of a reference clock. In other words, the DLL circuit includes a variable delay circuit that delays the reference clock to output a control clock having a predetermined timing, a phase comparison circuit that compares the phases of the reference clock and the control clock with each other and adjusts the amount of delay performed in the variable delay circuit so that the phases are matched with each other, and a delay control circuit.